Senior Analog IC Design Engineer
Senior Analog IC Design Engineer
Location: Kelowna, BC
Work experience 10-15 years
Expected Earnings $100,000 – $120,000 Salary + bonus + benefits
Our client designs and markets high performance video & audio semiconductors for the consumer entertainment, home & automotive markets. TM8 is helping them locate and secure a hands-on Senior Analog Design Engineer for their Design team. As a Senior Analog IC Design Engineer, you will be responsible for the specification definition, architecture, circuit design, layout supervision, and characterization of high-performance mixed signal circuits utilizing advanced CMOS technologies driving consumer electronics applications. Circuits include linear voltage regulators, data converters, OPAMPS, switching voltage regulators, bandgap circuits, transceivers, active filters, and PLL design blocks just to name a few. Other responsibilities will include supporting other groups for testing, qualifying and releasing designs to production.
Required Skills & Experience – Senior Analog IC Design Engineer
-Masters in Science in Electrical Engineering -10+ Years experience -You’re a great designer -Deep understanding & experience with Band Gaps, Level Shifters, PLL, Clock Generators, LNA, VCO, Closed Loop, High-Gain Amps -Creative -High level of SPICE expertise required -The ideal candidate will have a strong set of Analog IC design skills in a wide range of circuits. Strong layout knowledge and parasitic component understanding is a must. -Expertise with software tools such as Schematic entry, Matlab, etc. is desired. -Process and Device Physics knowledge is a strong plus. -Basic digital design skills at the gate level and utilizing Verilog are an added benefit.
***Specific Skills Required***
* Recognition of amplifier configurations at the block level: instant grasp of noise gain, signal gain and so forth.
* To be able to look at an op-amp drawing and describe the pole zero locations, know what product of what resistors and capacitors are creating the poles and zeros. Understand Open- Loop Characteristics, identify Phase Margin on a Bode plot, and know how phase margin varies with closed loop gain.
* Comprehend 1/f noise and its relation to gate area. Know that the noise of bipolar devices is re/2 and for a FET 2/3gm. Describe shot noise as distinct from voltage noise and explain its origin. Understand why input stage noise should dominate, optimize load networks for low noise.
* Comprehend, at the device level, dominant pole compensation and correctly identify the Gm and C that determine its value. Understand zero compensation techniques and its impact on excess phase.
* Know the limitations of R-2R networks, on-resistance errors etc. Correctly draw a R-2R network in both Voltage Mode and Current mode.
* Understand the first principles of Sigma-Delta modulation and correctly derive the STF and NTF for a block-diagram level Sigma-Delta modulator.
* Understand staticizer failure (meta-stability) and outline techniques to reduce it.
* Understand that a PLL is a second order system and what that means to the zero in the loop filter. Point out the optimum point for phase noise given a poor low frequency local oscillator and a good quality input clock. Know what a variable modulus pre-scalar does. Accurately describe what phase noise is, and how it scales with frequency,
* Understand the principle of a band-gap circuit and know the acronyms PTAT and ITAT, show a simple continuous time band-gap. Never having a seen a switch-cap band-gap nevertheless be able to identify the PTAT and ITAT aspect.
* Draw at least one implementation of a bi-quad stage of a filter; know why all filters are reducible to bi-quads. Understand what Q is, and the optimum placement of w,Q in a bi-quad chain for signal level issues.
*Explain why an RF signal is matched at the receiver and show an outline of how this is commonly achieved at the devices level.
*Draw schematics with ease, those drawing corresponding to signal from left to right (or rarely, visa-versa) and always with higher voltages at the top.